Switches are devices that establish connections between networks and perform packet switching in communication systems. A switch that relays communications of a plurality of information processing devices exists. Such a switch includes multiple ports so that the switch can connect to a plurality of information processing devices. A switch (hereinafter called a multiport switch) that includes multiple ports receives packets from a plurality of information processing devices and transmits packets to a plurality of information processing devices. In such a multiport switch, multiple ports share a memory. The reason for this is to, when a multiport switch performs what is called multicast transmission in which the same packet is transmitted to a plurality of information processing devices, prevent the multiport switch from making copies of a packet in response to the number of information processing devices to which the packet is transmitted. In a multiport switch, the processing speed of packet switching can be improved by using memory interleaving for the shared memory.
In a case where a multiport switch stores transfer data (a packet) in a shared memory, using memory interleaving, unless the input and output throughput of each port is set to be the same as the input and output throughput of a memory per port, a problem such as a decrease in the efficiency of storing operations on a shared memory occurs. That is, when the switch stores, in the shared memory, a gap occurs due to the difference in input and output speed between the ports and the shared memory. For example, when the data rate supplied from a port is smaller than the data rate consumed by the shared memory per port, padding data needs to be inserted in the shared memory, in order to match the both data rates. In such cases, even though the latency (delay time) can be shortened by interleaving, the efficiency of storing operations on the memory decreases by the padding data. Thus, in a multiport switch, in order to implement cut through processing in which transfer data is efficiently stored in a shared memory, using memory interleaving, and the latency (delay time) is short, the input and output throughput of each port needs to be set to match the input and output throughput of the shared memory per port, or the ratio between the input and output throughputs needs to be set to be an integral multiple.
However, in a multiport switch, setting the input and output throughput of each port to match the input and output throughput of a shared memory per port, or setting the ratio between the input and output throughputs to be an integral multiple significantly limits the variation of the configuration of the switch. For example, when the number of ports in a switch is increased, the total input and output throughput of the ports in the switch increases accordingly. To keep the efficiency of storing operations on a shared memory, the input and output throughput of the shared memory per port needs to be increased to an integral multiple of the input and output throughput of a port. Thus, in a multiport switch, it is desired that, without setting the input and output throughput of each port to match the input and output throughput of a shared memory per port or setting the ratio between the input and output throughputs to be an integral multiple, the efficiency of storing operations on the memory is not decreased by avoiding padding data being stored in the shared memory, and the latency is shortened.
Japanese Laid-open Patent Publication No. 2004-240980 discloses techniques for using shared memories in switches that perform packet switching.